1. Field of the Invention
This invention relates to the field of electrochemical deposition and removal of copper, and, more particularly, to electrochemically polishing copper films.
2. Background of the Invention
In the manufacture of devices on semiconductor substrates, such as semiconductor wafers, multiple levels of conductive layers are applied to the substrate. In order to fabricate features, circuits, vias and devices on the substrate, various techniques are used to deposit and etch materials on the substrate. Deposition techniques include processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and immersion of the substrate into an electrolyte solution. This last technique may be used for either electroless deposition or electroplating.
Similarly, a number of techniques are known for removing a material from a wafer. These techniques include wet chemical etching, reactive ion etching (RIE), plasma etching, chemical mechanical polishing (CMP), and immersion of the wafer into an electrolyte solution. Material removal by subjecting an immersed wafer to an electrolyte employs equivalent equipment set-up to that used for electroplating, but with an opposite result because charged particles are removed from, rather than deposited onto, the wafer.
Plating systems, in which an object is immersed in a plating solution to plate metal onto the object, are well known in the art. A variety of metals can be plated by simple immersion, or electroplated when electrodes are introduced into the solution. In copper plating, a plating solution such as a mixture of copper sulfate (CuSO4) and sulfuric acid (H2SO4) is used as the source of copper to plate copper onto an object. Typically, a cathode is connected to the object that is to be plated (so that the object functions as the cathode electrode) and a potential is placed across the cathode and an anode. Copper ions in the solution will then be reduced onto the cathode electrode (namely, the object to be plated).
In the traditional copper plating approach, the anode electrode is usually made of copper, which dissolves into the plating solution to replace the copper ions as the copper ions are depleted. However, for precision plating, inert anodes are used so that the anode does not change shape during the plating process. Instead of the copper ions being oxidized from the anode material, some other source of copper is needed. In this instance, copper containing material is introduced into the plating solution. That is, an external source is used to replenish copper ions in the solution as the copper ions are depleted from the solution due to the plating action.
Traditional complementary metal oxide semiconductor (CMOS) integrated circuits have been based on aluminum conductors and a silica (SiO2) dielectric. As devices become faster and more complex, the conductors on the chip must occupy less space, and become narrower and narrower. Conductors of less than 0.25 microns are common, and current targets are for conductors of 0.13 microns to 0.1 microns or smaller. Low dielectric constant materials are also being developed to replace the standard SiO2 dielectric to reduce the capacitance associated with the conductive lines. A wide variety of low K dielectric materials have been studied, such as F- and C-doped silicate glass, polymers such as polyarylether and polyimides, and porous versions of these materials, including xerogels and aerogels.
Copper metallization processes have been developed to replace the traditional aluminum interconnect. Copper has about two-thirds the electrical resistance of aluminum, making copper a much better conductor. In addition to low resistance, copper exhibits higher interconnect speed and higher resistance to electron migration. P. Singer, xe2x80x9cTantalum, Copper and Damascene: The Future of Interconnectsxe2x80x9d, Semiconductor International, June 1998.
Currently, copper is applied to silicon semiconductor substrates or wafers with either a single or dual damascene metallization process. In a typical metallization process: (0) conductor trenches or via holes are etched into a dielectric layer, which can be standard SiO2 or another low K permitivity dielectric material, on a semiconductor substrate; (1) an interface barrier layer is deposited on the substrate using PVD or chemical vapor deposition (CVD); (2) a copper seed layer is deposited onto the barrier layer using PVD or CVD; next (3) copper is deposited by electrochemical deposition (ECD), typically with an acidic copper electroplating solution, to fill in the features, such as via holes and conductor trenches, on the semiconductor substrate; finally (4) excess copper and barrier layer materials are removed from the field region using a chemical mechanical planarization (CMP) process. Dresher W. H., xe2x80x9cSpeeding-up your computer in the 21st century using Copper ICsxe2x80x9d.
The diffusion barrier is used to prevent copper from migrating into the dielectric material and into the silicon substructure of the semiconductor substrate. Examples of the barrier layer materials are cobalt, chromium, nickel, palladium, tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, tungsten silicon nitride, tantalum silicon nitride, among others. Examples of the dielectric materials are silicon dioxide (SiO2), F- and C-doped silica glass, silica aerogels, xerogels and organic polymers. Some of these example low-K dielectric materials are porous and have low mechanical strength. The mechanically weaker low-K materials make them incompatible with standard chemical-mechanical polishing (CMP) methods currently used in ULSI manufacturing processes because these materials are prematurely removed with the copper during the CMP process that is intended to remove only the excess copper and barrier layer. An improved process for polishing copper is needed.
As is known in the art, CMP is a semiconductor fabrication technique using (a) a chemical solution that contains a slurry, and (b) a polishing pad. The chemical solution and pad are applied to the wafer to planarize or remove excess material from the wafer surface. One disadvantage of CMP processes is that too much copper or dielectric material may be removed from regions on the semiconductor substrate when polishing continues too long. The excessive removal of copper is called xe2x80x9cdishingxe2x80x9d and the excessive removal of dielectric material is called xe2x80x9cerosion.xe2x80x9d The relative softness of the copper as compared to the substrate surfaces can make it difficult to detect the proper end-point for the CMP process.
Standard methods for electro-polishing or Electro-Chemical Polishing (xe2x80x9cECPxe2x80x9d) copper are usually performed in an acidic solution, such as phosphorous acid. A relatively great amount of material is removed from the wafer in order to obtain a smooth surface. Electro-polishing in acid to remove great amounts of copper is not compatible with copper metallization processes used in ULSI fabrication, where the deposited copper layer usually is quite thin (e.g., 1 xcexcm). One goal of the present invention is to obtain a very smooth surface by removing less than one micrometer of copper material from the substrate. Another goal is to set and try to reach a clearly defined end point to stop the electro-polishing process at the interface between the copper and the barrier layer. Excessive xe2x80x9cdishingxe2x80x9d of the copper surface should be avoided where possible.
Methods for electrochemical polishing of copper films on semiconductor substrates for integrated circuit fabrication to remove copper material without chemical-mechanical-polishing (CMP) are disclosed. A semiconductor substrate with a copper film residing thereon is immersed in an alkaline solution (pH above 7). The alkaline solution contains cyanide, copper salts, such as CuCN, complexing agents, such as KCN, a base, such as KOH, a buffer agent, such as Na2CO3 (Na can be used to replace K) and organic additives, such as wetting agents and grain refiners. A cyanide-free solution is preferred for safety and environmental reasons. A cyanide-free alkaline solution contains copper salts, such as CuS4 or copper pyrophosphate, a complexing agent, such as pyrophosphate or ethylenediamine, a base such as NaOH or KOH, and organic additives. In some semiconductor applications, mobile ions, such as Na+ or K+, are not preferred, so an organic base, such as NH4H may be used in place of base solutions containing Na+ and K+. Thus the alkaline solution may contain one or more of copper salts, copper sulfate, copper pyrophosphate, alkali metal pyrophosphates, including sodium pyrophosphate, ammonium pyrophosphate, orthophosphate, sodium hydroxide, potassium hydroxide, ammonium hydroxide and ethylenediaminetetraacetic acid.
A counter electrode is placed in contact with the alkaline solution. To remove copper material from the copper film and thereby polish the film surface, the copper film forms the anode, and the counter electrode forms the cathode. A constant current is applied, preferably with a current density from 5 to 100 amperes per square foot, most preferably from 5 to 30 amperes per square foot. The alkaline solution is maintained preferably at a temperature of 70xc2x0 F. or above, most preferably in the range of 70xc2x0 F. to 150xc2x0 F.
The end point of the copper removal method is best detected by monitoring the applied voltage. An increase in the voltage indicates that the remaining copper film is becoming very thin. A sudden increase in the voltage indicates that all copper has been completely removed and the barrier layer surface, such as tantalum nitride (TaN), for example, is exposed. The barrier layer, usually Ta or TaN, does not dissolve in the electro-polishing solution. Because the barrier layer is conductive, but has a much higher resistivity than copper, a jump in voltage occurs when the copper film is gone.
The method of the invention produces a very smooth copper surface on the substrate after removing only a relatively small amount of copper (usually less than one micrometer). The method also stops removing materials on the barrier layer, thus giving a clear end point to the polishing. An additional advantage of the electrochemical polish method of the present invention is that it may be used also to deposit copper selectively onto an existing copper film, thereby to improve the quality of the film surface. By reversing the electrode potential (by making the wafer surface a cathode electrode), copper will plate on the exposed copper surface, but not plate on the exposed barrier layer surface, such as a tantalum (Ta) or tantalum nitride (TaN) layer. When depositing copper in this manner, the copper material does not deposit onto the barrier layer. CMP processes can remove a greater amount of copper from the central portion of a copper trench leaving a dished surface. If not controlled properly, electro-polishing processes may also remove more copper material than intended to leave a dished surface. Using the method of this invention, but reversing the direction of the current, copper may be deposited selectively onto the dished surface to restore the planarity of that surface. Therefore, multiple cycles of deposition and etching can be implemented to produce desired surface conditions.